Silicon and FPGA

Verilog to a gate-level netlist, for both FPGA and ASIC targets. The anchor of the whole open flow.

Start with

yosys -p "read_verilog top.v; synth_ice40 -top top -json top.json"

The gotcha

SystemVerilog support is partial. Check what your constructs lower to before assuming they synthesized.

First thing I run on unfamiliar RTL. The linter alone catches more than most testbenches.

Start with

verilator --lint-only -Wall top.v

The gotcha

It is a two-state cycle simulator, so it will not show you X propagation. Use an event simulator when that matters.

Testbenches where timing and X states matter, which Verilator deliberately does not model.

Start with

iverilog -o sim tb.v top.v && vvp sim

The gotcha

Slower than Verilator by orders of magnitude. Use it for correctness, not for regression volume.

Writing stimulus and checks in Python against any simulator, instead of in SystemVerilog.

Start with

make SIM=icarus

The gotcha

Coroutine timing is the learning curve. Get one trivial test passing before writing a real one.

Takes the Yosys netlist to a bitstream, with Project IceStorm, Trellis or X-Ray behind it.

Start with

nextpnr-ice40 --up5k --package sg48 --json top.json --asc top.asc

The gotcha

Timing closure is less aggressive than vendor tooling. Leave margin in the constraint.

Floorplan, placement, clock tree and routing against an open PDK. LibreLane is the FOSSi Foundation successor to OpenLane 2, which lost its home when Efabless closed.

Start with

python3 -m librelane --pdk-root $HOME/.ciel ./config.json

The gotcha

Invoked as a Python module, and the flag is --pdk-root pointing at the PDK directory, not a PDK name. Most tutorials you will find still drive the original OpenLane; the flow steps are the same and the invocation is not.

Viewing GDS, running design rule checks, and extracting for LVS alongside netgen.

Start with

klayout -e layout.gds

The gotcha

A clean open DRC run is not foundry sign-off. Budget a commercial check before committing to a mask set.