Capabilities - VLSI, ASIC, FPGA

Semiconductor and programmable logic

Most consultancies cannot help you below the operating system. I can.

What that means in practice

ASIC design flow: RTL through synthesis, timing verification and sign-off
Scan-chain insertion, design for test and yield considerations
Floor planning, place and route, pad-frame and packaging preparation
Sub-micron CMOS process targeting and foundry submission readiness
FPGA architecture, implementation and timing closure
Hardware security review where the threat model reaches the die

Depth: Lead-engineer-level responsibility for complete flows, from register transfer description through to a netlist accepted for fabrication.
Who I bring in: Foundry and shuttle services, packaging houses, semiconductor test partners.
Scoping this: Silicon decisions are expensive to reverse. Scope a review before tape-out, not after.

Where I write about this

The newsletter follows what is changing here: one drawing, one decision worth revisiting, one tool used in anger, and what I am seeing across the network. Research worth reading gets cited when it changes a decision.

Ask about semiconductor and programmable logic

Adjacent

Rarely just one domain.

Most engagements touch three or four. These are the ones that usually come with it.